1. Technical Field
The present invention relates to a semiconductor non-volatile memory, a charge accumulating method for a semiconductor non-volatile memory, and a charge accumulating program storage medium. The present invention particularly relates to a semiconductor non-volatile memory that applies a voltage plural times between a gate electrode and at least one of a source electrode and/or a drain electrode until an amount of charge accumulated in an charge accumulating section becomes a specific value, and changes the voltage application state such that the charge accumulating amount per time is increased as the number of times of voltage application increases. The present invention also particularly relates to a charge accumulating method and a charge accumulating program storage medium of such a semiconductor non-volatile memory.
2. Related Art
Conventionally, there is a semiconductor non-volatile memory that has two charge accumulating sections provided in a single memory cell, and can store 2-bit data in a single memory cell by storing data of two values (“0” or “1”) in the respective charge accumulating sections.
For example, a semiconductor non-volatile memory is disclosed in Japanese Patent Application Laid-Open (JP-A) No. 2005-64295 having a structure in which two charge accumulating sections made from a silicon nitride film are formed physically discontiguous to each other at the two outside faces of the gate electrode of a memory cell.
In a semiconductor non-volatile memory of such a structure, 2-bit data can be stored in a single memory cell by storing data of two values, 0” or “1”, in the respective charge accumulating sections of the memory cell. FIG. 23 is a schematic diagram of a memory cell of the semiconductor non-volatile memory described in JP-A No. 2005-64295 showing the states that can be adopted thereby. Namely, the initial state is one in which there is no charge (electrons) accumulated in each of the charge accumulating sections of the memory cell, corresponding to data “1”, and a state in which charge has been accumulated corresponds to data “0”. 2-bit data can thereby be stored in a single memory cell.
Writing to, reading from, and erasing in the semiconductor non-volatile memory of such a structure are respectively performed in the following ways.
For example, consider the case where, as described above, the initial state in which there is no charge accumulated in the charge accumulating sections corresponds to data 1, and the state in which charge is accumulated in the charge accumulating sections corresponds to data “0”. In such a case, writing data “0” to the drain side is firstly performed by application of a positive voltage to the drain region (drain electrode), application of a positive voltage to the gate electrode, and connecting the source region to ground potential. By so doing, hot electrons are injected into the charge accumulating section at the drain side, resulting in data “0” being written.
Reading the data of the drain side is performed by applying a positive voltage to the source region, applying a positive voltage to the gate electrode, and connecting the drain region to the ground potential. When there is no charge accumulated in the charge accumulating section of the drain side, sufficient read current value is obtained. In such a case, determination is made that data “1” is written therein. However, when there is charge accumulated in the charge accumulating section of the drain side, the read current value is low. In such a case, determination is made that data “0” is written therein. In this manner, two values of data “0” and “1” are discriminated between by whether or not the read current value is a specific value or greater.
Erasing of data on the drain side, namely operation to return to the initial state in which there is no charge accumulated in the charge accumulating section (the state corresponding to data “1”) is performed by applying a positive voltage to the drain region, applying 0 or a negative voltage to the gate electrode, and placing the source region in an open state (floating state). By so doing, hot holes generated in the periphery of the drain region are injected into the charge accumulating section, and data erasure can be performed by neutralizing the charge accumulated in the charge accumulating section. Note that erasure of data can also be accomplished by irradiation of ultraviolet radiation or by heat treatment.
In this manner, the semiconductor non-volatile memory of the structure described in JP-A No. 2005-64295 discriminates between the two values of data “0” or “1” according to the magnitude of the read current value. Ideally the read current value adopts the same values, according to “0” or “1” data, for all of the memory cells. However, in practice a degree of variation occurs for each of the memory cells due to circumstances, such as variations in processes and the like.
FIG. 24 is a graph showing, in a integration of plural memory cells, read current values on the horizontal axis, and showing the number of individual charge accumulating sections of memory cells that adopt each of these read current values on the vertical axis. The distribution (current value distribution) is thereby shown, centered on the theoretical current value according to the data of “0” or “1”, respectively. Note that the range of current values of a given width between the distribution (current value distribution) of the charge accumulating sections expressing data “0” and the distribution of the charge accumulating sections expressing data “1” is referred to as the “current window”. In order to discriminate correctly between whether “0” or “1” has been written, the current value distribution width needs to be narrow, and for a current window of sufficient width to be present. Recently, attempts have started to try and realize storage of 4-bit data in a single memory cell, in a semiconductor non-volatile memory provided with two charge accumulating sections for each memory cell.
For example, in the article “4-bit per Cell NROM Reliability”, by Boaz Eitan and 11 others, published in IEEE International Electron Devices Meeting 2005: iedm Technical Digest: Washington, D.C.: Dec. 5 to 7, 2005, USA, IEEE, 2005, Session 22.1, a structure is described with charge accumulating section at both ends of a single silicon nitride film formed contiguously below a gate electrode of a memory cell, and 4-bit data is stored per single memory cell by storing data of 4 values (“00”, “01”, “10”, in sequence from the greatest charge accumulated, and “11” with no charge accumulated”). Furthermore, the importance of taking countermeasures against cross talk between the two end sections of the cell, and the need to ensure that correct writing is performed, is reported therein.
Writing 4-bits to each of the respective cells at the same time is reported as a countermeasure against cross talk. Performing two stages of writing is reported as a specific example of a writing method. The two stages of writing are a first stage for performing fast writing, and a second stage for performing accurate writing. Writing is commenced at the first stage with a given drain voltage (3V in FIG. 4 of the above publication by Boaz Eitan et al.), and so-called drain stepping is performed, in which the drain voltage is gradually raised as the number of times of writing increases, and writing is ceased just before a respective charge accumulating section has reached the desired threshold value voltage. Writing is commenced at the second stage from a specific gate voltage (7V in FIG. 4 of the above publication by Boaz Eitan et al.), and the desired threshold value voltage is achieved in the respective charge accumulating sections by performing so-called gate stepping, in which the gate voltage is raised as the number of times of writing increases. It is reported that the accuracy of writing can be raised by this two stage writing.
A writing method of applying voltage and confirming the write amount (or the read current value) in sequence for each of the charge accumulating sections to give the desired write amount (or the read current value) by plural repetitions in this manner, is referred to as “verify writing”. In verify writing, a greater precision in the desired writing amount can be achieved, in comparison to methods in which the desired writing amount is made by a single voltage application.
However, there is a known problem, called word line disturbance, relating to writing in non-volatile memories, such as, for example, flash memories or the like (JP-A No. 10-27486). Word line disturbance is a phenomenon in which, during write operation of a bit, a high voltage is applied to non-selected memory cells with a common word line, leading to occurrence of a weak written (disturbed) state, so that the threshold voltage thereof fluctuates and the stored data is changed. A technique of writing in sequence from the memory cells requiring the deepest writing is reported in JP-A No. 10-27486 as a counter measure to word line disturbance.
In a semiconductor non-volatile memory provided with two charge accumulating sections per single memory cell, there is a problem that due to the writing operation of one of the charge accumulating sections, the read current value falls of the other of the charge accumulating sections in the same memory cell (referred to as the “mirror side”).
For example, in the semiconductor non-volatile memory of JP-A No. 2005-64295, when 2-bit data is stored per single memory cell, namely when data of two values “0” or “1” is stored in a single charge accumulating section, in a case where “0” is stored in one charge accumulating section (for example on the source side) from the two charge accumulating sections of a single memory cell, and “1” is stored in the other charge accumulating section (for example on the drain side). In order to store “0” in the source side, it is necessary to perform writing operation on the source side charge accumulating section, to trap charge. However, when writing operation is performed to the source side charge accumulating section, the read current value on the drain side becomes lower than the desired read current value. This is thought to be caused mainly by charge that has been accumulated on the source side charge accumulating section impeding the current flowing when reading operation is performed to the drain side.
Note that this problem is not limited to semiconductor non-volatile memories provided with two charge accumulating sections per single memory cell, and also occurs in semiconductor non-volatile memories provided with three or more charge accumulating sections per single memory cell. FIG. 25 is a graph showing a state in which, in an integration of plural memory cells, the read current value of the mirror side falls. In the graph, similar to in FIG. 24, the horizontal axis is the read current values, and the number of individual charge accumulating sections of memory cells that adopt each read current value is shown on the vertical axis. The solid lines show the read current value distribution (current value distribution) of data in the state prior to performing writing to the other of the charge accumulating sections in the same memory cell, and the broken line shows the data current value distribution (current value distribution) of the mirror side after writing has been performed to the other charge accumulating section in the same memory cell. In this manner, the current window between “0” and “1” gets narrower due to the read current value of “1” falling as a whole.
However, not only is there such a fall in read current value on the mirror side (FIG. 25), but also, as shown in FIGS. 26A, 26B, the current window is also made narrower due to the width of the current value distribution widening. Namely, if the gate current remains low, then due to there being memory cells that are not sufficiently written (charge is not sufficiently accumulated), as shown by A in FIG. 26A, the current value distribution width widens, and the current window becomes narrower. However, if in contrast, the gate current remains high, as shown by B in FIG. 26B, then due to there being memory cells that are over written (charge is over accumulated), the current value distribution width widens, and the current window becomes narrower.
From this standpoint, if 2-bit data is stored per memory cell then by raising the precision of writing by verify writing as described above, the read current value distribution width can be made narrow, and a certain degree of current window can be secured.
However, when 4-bit data is stored per memory cell in a semiconductor non-volatile memory provide with two charge accumulating sections per single memory cell, then data of 2-bits (4 values) are written to each of the charge accumulating sections. For example, FIG. 27 is a schematic diagram showing the states that should be adopted by each of the charge accumulating sections of a memory cell when data of 4-bits per single memory cell is stored in the semiconductor non-volatile memory described in JP-A No. 2005-64295. Furthermore, FIG. 28 is a graph showing an ideal read current value distribution in an integration of plural memory cells, with the read current value on the horizontal axis, and the number of individual memory cells that adopt each read current value on the vertical axis. In this manner, the current window becomes narrower than where there are two bits per single memory cell.
Therefore, as shown in FIG. 29, when the read current value falls on the mirror side, it is difficult to secure a current window to perform verify writing. For example, consider the read current value when the initial state of one of the charge accumulating sections is the “11” state. In such a case, although a fall in the read current value does not occur when the other charge accumulating section is also in the “11” state, if the other charge accumulating section has “00” data written therein, the read current value of the first charge accumulating section falls. Therefore, the current window between “10” and “11” gets narrower. Since a phenomenon like this occurs for all data, it is difficult to secure sufficient current window.
Note that in FIG. 29, the solid lines show the distribution of data read current values of the first charge accumulating section prior to performing writing to the other charge accumulating section in the same memory cell, and the broken lines show the distribution of data current values in the first charge accumulating section after writing has been performed to the other charge accumulating section in the same memory cell.
However, in order to make the above current value distribution widths narrower, in the technology of JP-A No. 2008-85196, the sequence of writing to the memory cells is made such that writing occurs in sequence from the memory cells for which the charge to be accumulated is the greatest. Namely, as shown in FIG. 30A, firstly writing is performed plural times, at the same respective time, to each of plural memory cells to which 00 is to be written, secondly writing is performed plural times, at the same respective time, to each of plural memory cells to which 01 is to be written, then finally writing is performed plural times, at the same respective time, to each of plural memory cells to which 10 is to be written.
In such cases, the gate voltage and the drain voltage (the source voltage similarly) change in the following manner. Namely, first, as shown in FIG. 30B, when 00 is being written to each of the memory cells, the gate voltage is gradually increased, from a starting value of 9.0V, as the number of times of writing increases, and is then made constant after it has reached 10.0V. Furthermore, when 01 is being written to each of the memory cells, the gate voltage is gradually increased, from a starting value of 7.5V, as the number of times of writing increases. Then when 10 is being written to each of the memory cells, the gate voltage is gradually increased, from a starting value of 7.0V, as the number of times of writing increases.
The drain voltage, as shown in FIG. 30C, is always constant (6.5V), independent of the number of times of writing.
In the technology of above JP-A No. 2008-85196, the drain voltage (the source voltage similarly) is gradually increased as the number of times of writing increases, however, since the drain voltage is constant, memory cells exist which have been excessively written, as shown in FIG. 21A, the current value distribution width H1 widens, and the current window becomes narrower.